This application relies for priority upon Korean Patent Application No. 2000-76377, filed on Dec. 14, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a flash memory device with NOR-type memory cells.
In speed of program and read operations, a NOR-type flash memory is far superior to electrically programmable and erasable non-volatile semiconductor memory device. Therefore, the NOR-type flash memory has been garnering warm response from users that require faster operation speed.
FIG. 1 shows a construction of a flash EEPROM cell. An N-type source region 3 and an N-type drain region 4 are formed on a P-type substrate or a bulk region 2 with a channel region interposed therebetween. A floating gate 6, which is insulated by an insulating layer 5 of 100 xc3x85 A or less, is formed on the P-type channel region. A control gate 8, which is insulated by another insulating layer 7, is formed on the floating gate 6.
Channel hot electrons are injected into a floating gate from a channel region adjacent to a drain region, programming an EEPROM cell. The hot electron injection is carried out by grounding a source region and a P-type bulk region, applying a high voltage (e.g., +10V) to a control gate, and applying a voltage (e.g., 5V-6V) fitted for creation of hot electrons to the drain region 4. If negative charges (injected hot electrons) are sufficiently accumulated to a floating gate, the floating gate has a negative potential, boosting up a threshold voltage in a sequential read operation. The reading operation is carried out by applying a suitable voltage (e.g., 1V) to a drain region, applying an optimum voltage (to distinguish an erased cell from a programmed cell) of 4.5V to the control gate, and applying a voltage of 0V to a source region and the P-type substrate. A threshold voltage distribution of the programmed cell generally has a range of 6V-7V, as shown in FIG. 2. In the P-type substrate that is electrically separated from a floating gate by an insulating layer, a channel is not created. Accordingly, the memory cell is read out as logic xe2x80x9cOFF statexe2x80x9d.
F-N (Fowler-Nordheim) tunneling is made from a floating gate to a bulk (P-type substrate), erasing the EEPROM cell. A conventional tunneling manner is performed by applying a negative high voltage (e.g., xe2x88x9210V) to an electrode of the control gate and applying a suitable positive voltage (e.g., +5V) to the bulk region. In this case, the drain region holds a high impedance state or a floating state in order to maximize an erase effect. Due to such a manner, a strong electric field is created between the control gate and the bulk region. The F-N tunneling is made then, discharging negative charges in the floating gate to the source (or bulk). Generally, when an electric field of 6-7MV/cm is created across an insulating layer, the F-N tunneling is made. A thin insulating layer of 100xc3x85 or less is formed between the floating gate and bulk region, making the F-N tunneling. A threshold voltage distribution of the erased cell generally has a voltage range of 1V-3V, as shown in FIG. 2. In the reading operation, a channel is created in the P-type substrate that is electrically separated from a floating gate by an insulating layer. Accordingly, the memory cell is read out as logic xe2x80x9cON statexe2x80x9d.
When a memory cell array is constructed using the EEPROM cells, bulk regions of the cells are coupled to each other in order to achieve high integration. This causes a plurality of EEPROM cells sharing a bulk to be erased at the same time in the erasing operation. In this case, a region being an elementary unit of erasure is called a xe2x80x9cblockxe2x80x9d or a xe2x80x9csectorxe2x80x9d. Voltages each being applied to a terminal in reading and erasing operations is illustrated in the following [TABLE 1]. And, a distribution of cell threshold voltages after programming and erasing operations is shown in FIG. 2.
In a semiconductor memory device using NOR-type flash memory cells, programming and erasing operations are carried out by a command that is applied from an exterior of a chip. At this time, a verifying operation is carried out by an internal algorithm so that programmed or erased cell can have target program or erase threshold voltage distribution. If a cell is under or over a target threshold voltage, the cell is subject to a re-programming operation and a re-erasing or over-erase repair post-programming operation. An embedded algorithm for erasing a sector is classified into three parts that are a pre-programming algorithm as a first programming operation, a main erasing algorithm, and a post-programming algorithm as a second programming operation, as shown in FIG. 3.
The embedded algorithm proceeds, as follows. In order to collect a threshold voltage distribution of an erased cell, all cells in a corresponding sector are sequentially programmed in the first programming operation to situate a threshold voltage of all cells in a sector, which will be erased, to a constant level (e.g., 7V or higher). A constant negative voltage (e.g., xe2x88x9210V) is then applied to all wordlines in the sector, erasing the cells at the same time as the main erasing operation. In this case, a constant positive voltage (e.g., 5V) is applied to not only a bulk of the corresponding sector but also a bulk of a cell in a redundancy field, erasing the cell at the same time as the cells in a main field. After the erasing operation, over-erased cells are detected to carry out a programming operation as the second programming operation for boosting up a voltage level thereof to a constant threshold voltage (e.g., 1V or higher) or higher.
Generally, a cell array of a NOR-type flash memory device is composed of redundancy fields for repairing cells whose programming and erasing operations are failed by hard defect and soft defect that occur in a main field and its cell array. In this case, a repaired unit is composed of row or wordline units or column or bitline units according to a core structure.
Cells causing a fail in a main field, which will hereinafter referred to as xe2x80x9cdefect cellsxe2x80x9d, are repaired by cells in a redundancy field, hereinafter referred to as xe2x80x9credundant cellsxe2x80x9d. In spite of the repair, the defect cells still remain in the main field, having an influence on operations of a memory device. In case of a wordline-related fail such as a wordline to bitline short, when a switch to decode a wordline is made using PMOS and NMOS transistors, a positive high voltage applied to a bulk during the erasing operation is equivalently applied to a gate. Thus, a voltage applied toward a drain of a PMOS transistor used in a conventional decoder is higher than that of a bulk in the PMOS transistor. A forward bias is then applied to a P-N junction. If a wordline is electrically connected to a bulk, the forward bias is also applied to a PMOS transistor junction used in a decoder. Accordingly, a wordline repair operation cannot be carried out in such a structure with an erasing operation is carried out by applying a bias to a bulk. This will be explained later in detail.
FIG. 4 schematically shows a 16M NOR-type flash memory device in accordance with a prior art. Also, FIG. 5 shows a wordline select signal in accordance with a prior art. In a 16M NOR-type flash memory device, to select one wordline during reading or programming operation, one sector is selected by a sector address. Generally, one sector has a storage capacity of 64 KB and is composed of 1024 wordlines and 512 bitlines. To decode 1024 wordlines after selecting one sector, conceptually, a 10-bit address is required. The 10-bit address is divided into a first address A0-A6 and a second address A7-A9, which are composed of seven address bits and three address bits, respectively.
Based on the first address, one of first select signals nSSi (i=0-127) for each selecting 128 selectors is activated. Also, based on the second address, one of second select signals PWLj (j=0-7) for selecting one of eight wordlines each corresponding to selectors is activated. Only one wordline corresponding to the activated select signals is selected. Since a voltage higher than a power supply voltage must be applied to a wordline in programming or reading operation, a level shifter is required which can switch a high voltage while decoding the wordline. With a sector unit, all cells of 64 KB are subject to the erasing operation at the same. Accordingly, a negative voltage is applied to wordlines WL0-WL1023 of the whole sector. A wordline select switch circuit with a structure for applying positive and negative voltages according to each mode is shown in FIG. 5. The wordline select switch circuit transfers a positive voltage to a wordline selected in programming or reading operation, or transfers a negative voltage to a wordline selected in an erasing operation.
If a wordline-related defect occurs in a memory array with such a structure, cells in a main field are repaired by cells in a redundancy cell. In other words, if an address is applied for externally accessing to a cell that adheres to a defect wordline, an internal logic circuit checks whether a wordline corresponding to the applied address is repaired. If it is then verified that the wordline is repaired, a redundant cell is applied by the address instead of a main cell. And then, all voltage conditions applied to the main cell are identically applied to cells in the redundancy field. In FIG. 5, a core uses a wordline select switch using both PMOS and NMOS transistors. When a wordlines is coupled to a bitline or a wordline is electrically coupled to a bulk, a positive voltage applied to the bulk in the erasing operation is applied to the wordline select switch. Due to the applied positive voltage, a forward bias is applied to a drain-bulk junction of a PMOS transistor in a wordline select switch where 0V is applied to a gate, a source, and a bulk in order to retain a turn-off state in the erasing operation. Thus, the device cannot be used.
To make matters worse, breakdown occurs between a bulk-drain junction and a bulk-source junction of an NMOS transistor in a wordline select switch for applying a negative voltage to a gate. More specifically, in case of wordline-bitline connection, a positive high voltage applied to a bulk in an erasing operation is boosted as much as a built-in voltage. The boosted voltage is applied to a bitline and a wordline, respectively. A voltage on a wordline is applied to a drain of the NMOS transistor, causing a breakdown between bulk-drain junctions of an NMOS transistor to which a negative voltage is applied. Thus, the device cannot be used. Such a problem is inevitable because a negative voltage is equivalently applied to a well of an NMOS transistor in order to form an NMOS switch to carry the negative voltage, and a breakdown voltage of a pocket P-well structure separated from an essential P-type semiconductor substrate is low due to a high concentration of a pocket P-well area.
In order to solve the foregoing problems, the present invention provides a non-volatile semiconductor memory device with a wordline select switch that is composed only using an NMOS transistor. The memory device with the wordline select switch can repair defects such as wordline-bitline connection, wordline-bulk connection, and wordline-wordline connection.
In accordance with the invention, a non-volatile semiconductor memory device is made of memory cell arrays each including a plurality of local wordlines, a plurality of bitlines, and a plurality of flash EEPROM cells located at intersections of the plural wordlines and bitlines. A plurality of global wordlines is arranged through the memory cell array, each corresponding to the local wordlines. A global decoder circuit is coupled to the global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to the local wordlines, and have wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select circuit. The global decoder circuit generates a control signal, based upon address information for selecting the memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordlines. The plural depletion MOS transistors are commonly controlled by the control signal. Each of the wordline select switches is made of two MOS transistors.